This invention relates to a method of fabricating a thinned CCD.
A charge-coupled device (CCD) may be made by processing a silicon die of p conductivity using conventional MOS technology to form a buried channel of n conductivity in an active region beneath the front side of the die (the side through which the die is processed). The channel is resolved into a linear array of like elementary zones by a clocking electrode structure which is composed of gate electrodes and overlies the front side of the die, and by application of selected potentials to the gate electrodes, a charge packet present in a given elementary zone of the channel may be advanced through the linear array of elementary zones, in the manner of a shift register, and discharged from the channel. In a multi-phase CCD, the gate electrodes are organized as multiple sets and different phases of a multi-phase clock signal are applied to the respective sets of gate electrodes.
Charge may be generated in the channel photoelectrically. Thus, if electromagnetic radiation enters the buried channel, it may cause generation of conduction electrons, and these conduction electrons may be confined in one of the elementary zones to form a charge packet.
A CCD may be used to generate an electrical signal representative of the distribution of light intensity over the active region of the CCD. In such an imaging CCD, there may be multiple imaging channels extending parallel to one another and each connected at one end to a common readout channel which extends perpendicular to the imaging channels. Charge packets are generated in the elementary zones or pixels of the imaging channels during an integration interval. Subsequently, during a readout interval, the charge packets are transferred from the imaging channels into the readout channel and the charge packets are transferred serially through the readout channel to an output amplifier.
A known method of fabricating a three-phase imaging CCD will now be described with reference to FIGS. 3-6.
FIG. 3 shows a silicon die 2 that has been processed in conventional fashion to form an active region 4 which extends partly into the die from the front side 6 thereof. The active region contains the imaging channels and the readout channel, but the channels are not shown in FIG. 3. The active region 4 is surrounded by a thick layer of field oxide 8. There are several apertures 10 (only one of which is shown in FIG. 3) in the field oxide. There is a thin layer of gate oxide (not shown in FIG. 3) over the die in the active region 4 and in the apertures 10.
Referring to FIG. 4, the clocking electrode structure includes three sets of polysilicon conductor strips 12.sub.1, 12.sub.2 and 12.sub.3, corresponding respectively to the three phases of the clock signal used to operate the CCD. The conductor strips 12.sub.1, 12.sub.2 and 12.sub.3 include respective gate electrodes 14.sub.1, 14.sub.2 and 14.sub.3 (FIG. 6) which extend over the thin oxide 16, crossing the channels that are influenced by the gate electrodes. Each conductor strip 12 includes a gate extension 18 (FIG. 5) which extends some distance over the field oxide. The conductor strips 12 of the three sets are formed sequentially, by depositing and patterning three successive layers of polysilicon, and the three deposits of polysilicon are referred to as the first, second and third levels, in accordance with the order in which they are deposited. Referring to FIGS. 4 and 5, the first level polysilicon also defines a polysilicon bus 20 which is formed on the field oxide 8 and interconnects the conductor strips 12.sub.1, of the first level polysilicon. The conductor strips 12.sub.2 of the second level polysilicon partially overlap the conductor strips 12.sub.1, of the first level polysilicon, but are not connected by a bus formed by the second level polysilicon. Similarly the conductor strips 12.sub.3 of the third level polysilicon partially overlap the conductor strips 12.sub.1, and 12.sub.2 but are not connected by a bus formed by the third level polysilicon.
Referring to FIG. 5, discrete islands 22 of polysilicon are deposited over the field oxide near the periphery of the die and extend into the apertures 10 in the field oxide.
When the polysilicon is initially deposited and patterned, it is non-conductive. Conductivity is imparted to the polysilicon conductor strips 12, the polysilicon bus 20 and the polysilicon islands 22 by doping with a donor dopant, such as phosphorus. The doping of all three levels takes place simultaneously, after all three levels of polysilicon have been deposited and patterned. In order to ensure that the conductor strips 12 and the bus 20 are electrically continuous, it is necessary to ensure that a conductor of an upper level does not cover the entire width of a conductor of a lower level and thereby mask the conductor of the lower level from the dopant source over its entire width. Consequently, the conductor strips of the second and third levels terminate short of the bus 20 so that they will not mask the bus 20. This is also why the second and third levels do not include buses since a second or third level bus would cover a conductor strip 12 of at least the first level over its entire width.
After the three levels of polysilicon have been deposited and doped, a layer 30 of reflow glass is deposited over the upper surface of the device, leaving portions of the polysilicon bus 20, terminal portions of the second and third level polysilicon conductor strips 12.sub.2 and 12.sub.3 and the polysilicon islands 22 exposed. Metal is deposited over the reflow glass to provide first, second and third buses 32.sub.1, 32.sub.2 and 32.sub.3. The first metal bus 32.sub.1, overlies the polysilicon bus 20 and is connected thereto by metal vias 34.sub.1, extending through apertures in the reflow glass. The second metal bus 32.sub.2 extends parallel to the first metal bus and is connected to the individual conductor strips 12.sub.2 of second level polysilicon by metal vias 34.sub.2 extending through apertures in the reflow glass. Similarly, the third metal bus 32.sub.3 extends parallel to the first metal bus and is connected to the conductor strips 12.sub.3 of third level polysilicon by metal vias 34.sub.3. Each of the metal buses 32 has a connection branch 36 extending outward to one of the polysilicon islands 22.
An interface layer 38 is deposited over the front side of this structure and a support 40 made of borosilicate glass is attached to the interface layer. The interface layer 38 accommodates differential thermal expansion between the silicon die 2 and the borosilicate glass support 40. The silicon die is then thinned from its back side to a thickness in the range from about 10 to 20 .mu.m. After thinning, the active region of the thinned die is masked and portions of the substrate outward of the active region are completely removed, leaving a silicon plateau 2' containing the active region surrounded by a plain of field oxide 8. In FIG. 5, the topography of the plateau and plain are inverted since, by convention, the front side of the structure is shown upward. The gate oxide is removed from the apertures 10 in the field oxide and aluminum bonding pads 42 are deposited into the apertures 10 and make contact with the polysilicon islands 22. The aluminum bonding pads are connected by wire bonding to external circuitry for driving the gate electrodes. See U.S. Pat. No. 4,923,825.
An important figure of merit of an imaging CCD is the charge transfer efficiency or CTE, which is a measure of the efficiency with which a charge packet which is formed in a given pixel of an imaging channel is transferred to the output amplifier at a given readout rate. In order to achieve a high value for the CTE, it is necessary that the relative potentials in the imaging channels or in the readout channel, induced by changes in the relative potential of the gate electrodes of the different phases, change in accurately predetermined manner and in accurately timed relationship.
The time required to charge and discharge the gate structure, so as to effect a change in potential in an imaging channel or the readout channel, depends on the resistance of the path from the bond pad to the gate electrodes. For a high speed application, where pixel data is read at multiple frames per second, this overhead time can be a significant part of the clock period and by decreasing this overhead time, it may be possible to increase the data rate without loss of CTE.
Owing to constraints in layout, the lengths of the connection branches from the metal buses 32 to the polysilicon islands 22 may be significantly different for the three metal buses respectively, and the connection branches may be connected to the respective metal buses at locations which are spaced apart along the metal buses: the connection branch for phase 1 may be connected to the metal bus 32.sub.1, at one end of the bus, the branch for phase 2 may be connected to the bus 32.sub.2 at the opposite end, and the branch for phase 3 may be connected to the bus 32.sub.3 midway between the two ends.
The metal buses 32 and their connection branches 36 are made of a refractory metal because of the high temperatures involved in forming the interface layer and the glass ceramic substrate. Refractory metals typically have substantially higher electrical resistivity than non-refractory metals that are commonly used in integrated circuit fabrication, such as aluminum. For example, the sheet resistivity of the refractory metal used in the conventional structure may be on the order of 5 ohms per square whereas the sheet resistivity of aluminum is 0.05 ohms per square. Some of the metal leads from the bond pads to the gates can be more than 100 squares, and accordingly the sheet resistivity of the refractory metal can have a substantial effect on device speed.
In a practical implementation of the CCD described with reference to FIGS. 3-6, the length of the metal bus is significantly different for the three phases. Consequently, at high clocking rates it is possible for the pulses of the different phases to be mistimed and for the charge transfer efficiency in the parallel section and/or the serial section to be impaired.